1. Field of the Invention
The present invention relates to radio frequency or microwave electronic power amplifiers, and more particularly to radio frequency or microwave electronic power amplifiers that may be controlled to produce two or more selectable output power levels for a particular input signal.
2. Related Art
Linear power amplifiers are often operated in class AB mode. Operation in class AB mode provides for reduced power supply current to the power amplifier as the power of the input signal is reduced. The power supply current can be reduced until a minimum quiescent current is reached. The direct current (DC) power to radio frequency (RF) power efficiency degrades as the power of the input signal is reduced. Some conventional linear power amplifiers provide an improvement in low power efficiency by stepping the quiescent current to a lower level for low power operation. However, the linearity of the power amplifier is degraded at very low quiescent current levels. This is described in more detail below in connection with FIG. 1.
FIG. 1 is a circuit diagram illustrating a conventional power amplifier 100, which includes amplifier stages 101-102 and associated bias circuits 111-112. Each of amplifier stages 101-102 includes a parallel-connected set of NPN bipolar transistors 103-104, respectively. Ballast resistors 105-106 are connected to the bases of transistor sets 103-104. In general, the bases of transistor sets 103-104 are configured to receive a radio frequency input signal (e.g., RFIN). The emitters of transistor sets 103-104 are coupled to ground, and the collectors of transistors sets 103-104 are configured to provide an RF output signal (e.g., RFOUT) to an output terminal of the associated amplifier stage.
When the input signal RFIN is controlled to be a high power signal (i.e., during high-power operation), a HI/LO control signal is activated to a first logic state. In response, bias voltage control circuits 111-112 provide relatively high bias voltages VBIAS1-VBIAS2. As a result, amplifier stages 101-102 operate in a linear manner in response to the RFIN signal. Conversely, when the input signal RFIN is controlled to be a low power signal (i.e., during low-power operation), the HI/LO control signal is deactivated to a second logic state. In response, bias control circuits 111-112 provide relatively low bias voltages VBIAS1-VBIAS2. Because the power amplifier transistors 103-104 in stages 101-102 are each biased uniformly, the current reduction represents a current density reduction in the constituent cells that comprise 103-104. Under these conditions, amplifier stages 101-102 consume less power, but the linearity of power amplifier 100 is degraded under these conditions.
Moreover, in both high power operation and low power operation, power amplifier 100 sees the same load impedance, RL. However, the optimum load impedance for high power operation is not the same as the optimum load impedance for low power operation. Because the load impedance is typically optimized for high power operation, the power amplifier exhibits degraded power efficiency during following deficiencies during lower power operation. This is significant in handset applications, since talk-time is dependent on efficient power amplifier operation.
A conventional Doherty amplifier, known since the 1930s, provides another way to increase amplifier efficiency. In a typical Doherty amplifier, an input signal to be amplified is split and follows two paths. The power split is typically half power in each path. The paths are later joined and the amplified signal is output to an antenna for transmission. Each path includes a phase delay component. A linear amplifier operates in one path. This linear amplifier is commonly referred to as the carrier amplifier, since Doherty amplifiers were originally designed for amplitude modulated (AM) signals. The carrier amplifier is typically designed to drive a load that is twice the impedance of the peaking amplifier for maximum amplifier efficiency of the carrier amplifier. A non-linear (e.g., class B or C) amplifier operates in the second path. This amplifier is commonly referred to as the peaking amplifier. The carrier and peaking amplifier are typically comprised of equivalent peak power capability amplifiers. When the input signal power to the Doherty amplifier exceeds an input threshold, the peaking amplifier begins to operate. At low power levels (e.g., unmodulated AM carrier level), the carrier amplifier operates efficiently. As the input power level increases to the level where the peaking amplifier begins to contribute significantly to the output power, the overall high efficiency is maintained since the peaking amplifier is operating in a naturally more efficient mode. Peaking amplifier operation lowers the effective load driven by the carrier amplifier, and the overall efficiency is maintained at a relatively high level. However, the Doherty amplifier provides somewhat non-linear amplification, which is unacceptable for certain signal transmissions, such as CDMA.
It would therefore be desirable to have a power amplifier that does not require an extremely low quiescent current density during low power operation (i.e., when the input signal power is relatively low), because such low quiescent current density results in non-linear amplification. It would be desirable for such a power amplifier to exhibit linear amplification. It would further be desirable for such a power amplifier to have an optimized load impedance for both high power operation and low power operation. The optimized load impedance raises the power efficiency of the amplifier while maintaining linear amplification.